//***********************************************************************
//
//      eb  q`r@`oh@ckk wb_`t@C
//
//      t@C  FFCSRASAPI.H
//              FckkgpAvP[VŃCN[h
//
//***********************************************************************


#ifdef FCSOFTRAS_EXPORTS
#define FCSOFTRAS_API __declspec(dllexport)
#else
#define FCSOFTRAS_API __declspec(dllimport)
#endif

// ̃NX FcSoftRas.dll GNX|[g܂


//***********************************************************************
// ֐`
//***********************************************************************

#ifdef __cplusplus          // C++CallČ`̊֐Callolɂ
extern  "C" {
#endif

FCSOFTRAS_API DWORD fcsoftrasOpen( VOID );
FCSOFTRAS_API DWORD fcsoftrasClose( VOID );
FCSOFTRAS_API DWORD fcsoftrasGetVersion( LPBYTE lpBuff, DWORD nBuffSize );
FCSOFTRAS_API DWORD fcsoftrasGetTemp( LPBYTE lpBuff, DWORD nBuffSize );
FCSOFTRAS_API DWORD fcsoftrasGetFan( LPBYTE lpBuff, DWORD nBuffSize );
FCSOFTRAS_API DWORD fcsoftrasGetFanInf( LPBYTE lpBuff, DWORD nBuffSize );
FCSOFTRAS_API DWORD fcsoftrasGetVoltage( LPBYTE lpBuff, DWORD nBuffSize );
FCSOFTRAS_API DWORD fcsoftrasGetHDDInf( LPBYTE lpBuff, DWORD nBuffSize );
FCSOFTRAS_API DWORD fcsoftrasGetMirrorStatus( BYTE byDriveNum, LPBYTE lpBuff, DWORD nBuffSize );
FCSOFTRAS_API DWORD fcsoftrasGetSMART( BYTE byDriveNum, LPBYTE lpBuff, DWORD nBuffSize );
FCSOFTRAS_API DWORD fcsoftrasGetPciError( LPBYTE lpBuff, DWORD nBuffSize );
FCSOFTRAS_API DWORD fcsoftrasGetRevRcn( BYTE byDriveNum, LPBYTE lpbyGetCnt );
FCSOFTRAS_API DWORD fcsoftrasSetRevRcn( BYTE byDriveNum, BYTE bySetCnt );
FCSOFTRAS_API DWORD fcsoftrasGetRTCTime( LPBYTE lpBuff, DWORD nBuffSize );
FCSOFTRAS_API DWORD fcsoftrasSetRTCTime( LPBYTE lpBuff, DWORD nBuffSize );
FCSOFTRAS_API DWORD fcsoftrasReleaseMirrorDrive( BYTE byDriveNum );
FCSOFTRAS_API DWORD fcsoftrasGetMirrorSMARTMode( BYTE byDriveNum, LPBYTE lpModeCode );
FCSOFTRAS_API DWORD fcsoftrasSetMirrorSMARTMode( BYTE byDriveNum, BYTE byModeCode );
FCSOFTRAS_API DWORD fcsoftrasGetHDDErrorLog( BYTE byDriveNum, LPBYTE lpBuff, DWORD nBuffSize );
FCSOFTRAS_API DWORD fcsoftrasGetHDDErrorLog2( BYTE byDriveNum, LPBYTE lpBuff, DWORD nBuffSize );
FCSOFTRAS_API DWORD fcsoftrasGetPowerButton( LPBYTE	lpBuff,	DWORD	nBuffSize);
FCSOFTRAS_API DWORD fcsoftrasClearPowerButton(void);
FCSOFTRAS_API DWORD fcsoftrasGetHDDIdentify (BYTE	byDriveNum,LPBYTE	lpBuff,DWORD	nBuffSize,LPBYTE  lpAtaCmd);
FCSOFTRAS_API DWORD fcsoftrasGetMirrorReconProgress (BYTE	byDriveNum,LPBYTE	lpModeCode);
FCSOFTRAS_API DWORD fcsoftrasDigitalIn(LPBYTE lpbyDigitalData);
FCSOFTRAS_API DWORD fcsoftrasDigitalOut(BYTE byDigitalData);
FCSOFTRAS_API DWORD fcsoftrasResetAndStartWDT(DWORD dwWdtTimerValue);
FCSOFTRAS_API DWORD fcsoftrasStopWDT(void);
FCSOFTRAS_API DWORD fcsoftrasExitWindows(UINT uFlags);
FCSOFTRAS_API DWORD fcsoftrasGetPowOffEvent( LPBYTE lpBuff, DWORD nBuffSize );
FCSOFTRAS_API DWORD fcsoftrasGetSSDStatus( BYTE byDriveNum, LPBYTE lpBuff, DWORD nBuffSize );

FCSOFTRAS_API DWORD fcrasRegisterAlarmApWindow(HWND );
FCSOFTRAS_API DWORD fcrasUnregisterAlarmApWindow(void);
FCSOFTRAS_API DWORD fcrasResetAndStartWDT(DWORD );
FCSOFTRAS_API DWORD fcrasStopWDT(void);
FCSOFTRAS_API DWORD fcrasGetStatus(LPBYTE );
FCSOFTRAS_API DWORD fcrasDigitalIn(LPBYTE );
FCSOFTRAS_API DWORD fcrasDigitalOut(BYTE );
FCSOFTRAS_API DWORD fcras7SegmentOut( BYTE );
FCSOFTRAS_API DWORD fcrasGetStatusX009(LPBYTE );
FCSOFTRAS_API DWORD fcrasExtLimitOut( BYTE ); 
FCSOFTRAS_API DWORD fcrasIntLimitOut( BYTE ); 
FCSOFTRAS_API DWORD fcrasGetExtLimit( LPBYTE );
FCSOFTRAS_API DWORD fcrasGetIntLimit( LPBYTE );
FCSOFTRAS_API DWORD fcrasSRAMWrite(LPBYTE);
FCSOFTRAS_API DWORD fcrasSRAMRead(DWORD dwOffset,LPBYTE lpbyDate,LPBYTE lpbyReadData);
FCSOFTRAS_API DWORD fcrasSRAMGetUserCurrent(LPDWORD lpdwOffset);
FCSOFTRAS_API DWORD fcrasSRAMGetSystemCurrent(LPDWORD lpdwOffset);
FCSOFTRAS_API DWORD fcrasSRAMWritePhy( DWORD,LPBYTE,DWORD );
FCSOFTRAS_API DWORD fcrasSRAMReadPhy( DWORD,LPBYTE,DWORD );
FCSOFTRAS_API DWORD fcrasSRAMInit(WORD dwMode);
FCSOFTRAS_API DWORD fcrasLCDOut(LPBYTE lpbyLcdData);

#ifdef __cplusplus
}
#endif


//***********************************************************************
// 萔`ꗗ
//***********************************************************************


// RETURNXe[^X
#define	FCSRASAPI_SUCCESS	0x00
#define	FCSRASAPI_DRVERR	0x01

// G[ڍ׏
#define FCRASERR			0x10000000
#define FCRASERR_OPEN		(FCRASERR | 1)


// FCRASײ ްޮݏ ް
#define LEN_VAR_MODELNUM	40			// ް      (ASCII 40)
#define LEN_VAR_FIRMREV		8			// ̧ѳ޼ޮ (ASCII  8)
#define LEN_VAR_SELIALNUM	20			// رް      (ASCII 20)

// HDD SMART ް
#define	LEN_SMART			512			// SMARTް = 512byte
#define	LEN_SMART2			1024		// SMARTް = 1024byte (ATTRIBUTE+THRESHOLD)

// HDD ErrorLog ް
#define PAGE_LEN_ERRLOG		512			// ErrorLog 1߰޻
#define PAGE_NUM_ERRLOG		64			// ErrorLog ߰ސ
#define PAGE_NUM_ERRLOG2	512			// ErrorLog ߰ސ2
										// ErrorLogް = 512x64byte
#define	LEN_ERRLOG			PAGE_LEN_ERRLOG*PAGE_NUM_ERRLOG
										// ErrorLogް = 512x512byte
#define	LEN_ERRLOG2			PAGE_LEN_ERRLOG*PAGE_NUM_ERRLOG2

// xװðޯď (fcsoftrasGetTemp)
#define TEMP_ERR_CPU	0x01			// CPUx    0: 1:װ
#define TEMP_ERR_INT	0x02			// x   0: 1:װ
#define TEMP_ERR_EXT	0x04			// Ox   0: 1:װ

// xܰݸ޽ðޯď (fcsoftrasGetTemp)
#define TEMP_WAR_CPU	0x01			// CPUx    0: 1:װ
#define TEMP_WAR_INT	0x02			// x   0: 1:װ
#define TEMP_WAR_EXT	0x04			// Ox   0: 1:װ

// ̧݉]װðޯď (fcsoftrasGetFan)
#define FAN_ERR_DATA1	0x01			// ̧1] 0: 1:װ
#define FAN_ERR_DATA2	0x02			// ̧2] 0: 1:װ
#define FAN_ERR_DATA3	0x04			// ̧3] 0: 1:װ
#define FAN_ERR_DATA4	0x08			// ̧4] 0: 1:װ
#define FAN_ERR_DATA5	0x10			// ̧5] 0: 1:װ

// ̧݉]ܰݸ޽ðޯď (fcsoftrasGetFan)
#define FAN_WAR_DATA1	0x01			// ̧1] 0: 1:װ
#define FAN_WAR_DATA2	0x02			// ̧2] 0: 1:װ
#define FAN_WAR_DATA3	0x04			// ̧3] 0: 1:װ
#define FAN_WAR_DATA4	0x08			// ̧4] 0: 1:װ
#define FAN_WAR_DATA5	0x10			// ̧5] 0: 1:װ

// dܰݸ޽ðޯď (fcsoftrasGetVoltage)
#define VOLT_WAR_DATA1	0x001			// d1      0: 1:װ
#define VOLT_WAR_DATA2	0x002			// d2      0: 1:װ
#define VOLT_WAR_DATA3	0x004			// d3      0: 1:װ
#define VOLT_WAR_DATA4	0x008			// d4      0: 1:װ
#define VOLT_WAR_DATA5	0x010			// d5      0: 1:װ
#define VOLT_WAR_DATA6	0x020			// d6      0: 1:װ
#define VOLT_WAR_DATA7	0x040			// d7      0: 1:װ
#define VOLT_WAR_DATA8	0x080			// d8      0: 1:װ

// HDD󋵂ޯď (fcsoftrasGetHDDInf)
#define HDDCONN_SMARTERR_BIT	0x01	// SMARTG[0:   1:ُ
#define HDDCONN_SSD_BIT			0x10	// SSD    0:ږ 1:ڗL(ݸ,װ)
#define HDDCONN_MRRTYPE_BIT		0x20	// װގ0:װ    1:װ
#define HDDCONN_CONNECT_BIT		0x40	// HDDڑ    0:ڑ 1:ڑL
#define HDDCONN_MIRROR_BIT		0x80	// װ    0:ڑ 1:ڑL

// ~[ð (fcsoftrasGetMirrorStatus)
#define HDDSTS_NORMAL			0x00	// 
#define	HDDSTS_ERR_DRV1			0x10	// װDrive1̏
#define	HDDSTS_ERR_DRV2			0x11	// װDrive2̏
#define	HDDSTS_ERR_DRV3			0x12	// װExtDrivȅ
#define	HDDSTS_ERR_DRV12		0x13	// װDrive1,Drive2̏
#define	HDDSTS_ERR_DRV13		0x14	// װDrive1,ExtDrivȅ
#define	HDDSTS_ERR_DRV23		0x15	// װDrive2,ExtDrivȅ
#define	HDDSTS_RECON_1			0x20	// ްč\z(Drive2Drive1ֺ߰)
#define	HDDSTS_RECON_2			0x21	// ްč\z(Drive1Drive2ֺ߰)
#define	HDDSTS_RECON_3			0x22	// ްč\z(ExtDriveDrive1ֺ߰)
#define	HDDSTS_RECON_4			0x23	// ްč\z(Drive1ExtDriveֺ߰)
#define	HDDSTS_RECON_5			0x24	// ްč\z(ExtDriveDrive2ֺ߰)
#define	HDDSTS_RECON_6			0x25	// ްč\z(Drive2ExtDriveֺ߰)
#define	HDDSTS_RECON_7			0x26	// ްč\z(Drive1ExtDrive,Drive2ֺ߰)
#define	HDDSTS_RECON_8			0x27	// ްč\z(Drive2ExtDrive,Drive1ֺ߰)
#define	HDDSTS_RECON_9			0x28	// ްč\z(ExtDriveDrive1,Drive2ֺ߰)
#define	HDDSTS_RECON_SKIP_1		0x30	// غݔ(Drive1)
#define	HDDSTS_RECON_SKIP_2		0x31	// غݔ(Drive2)
#define	HDDSTS_RECON_SKIP_3		0x32	// غݔ(ExtDrive)
#define	HDDSTS_RECON_SKIP_12	0x33	// غݔ(Drive1,Drive2)
#define	HDDSTS_RECON_SKIP_13	0x34	// غݔ(ExtDrive,Drive1)
#define	HDDSTS_RECON_SKIP_23	0x35	// غݔ(ExtDrive,Drive2)
#define	HDDSTS_ERR_RECON_1		0x40	// װDrive1̏,ްč\z(ExtDriveDrive2ֺ߰)
#define	HDDSTS_ERR_RECON_2		0x41	// װDrive1̏,ްč\z(Drive2ExtDriveֺ߰)
#define	HDDSTS_ERR_RECON_3		0x42	// װDrive2̏,ްč\z(ExtDriveDrive1ֺ߰)
#define	HDDSTS_ERR_RECON_4		0x43	// װDrive2̏,ްč\z(Drive1ExtDriveֺ߰)
#define	HDDSTS_ERR_RECON_5		0x44	// װExtDrivȅ,ްč\z(Drive2Drive1ֺ߰)
#define	HDDSTS_ERR_RECON_6		0x45	// װExtDrivȅ,ްč\z(Drive1Drive2ֺ߰)
#define	HDDSTS_PATROLRD			0x50	// ۰ذޒ

// PCIèװޯď (fcsoftrasGetPciError)
#define PCIERR_PARI				0x01	// PCIè  0: 1:װ

// SMARTӰ (fcsoftrasSetSAMRTMode)
#define SMARTMODE_DRVBRK_SMERR	0x01	// ײ1̏᎞ SMARTװ
#define SMARTMODE_ABORT			0x02	// ް (SMARTގt)
#define SMARTMODE_DRVBRK_NOSMERR 0x03	// ײ1̏᎞ SMARTװƂȂ
#define SMARTMODE_DRVBRK_ONESMOK 0x04	// ײ1̏᎞ ̂ݐ

// SSDװтޯď (fcsoftrasGetSSDStatus)
#define SSD_ALM_SPR		0x01			// ߱ۯ	0: 1:װ

// SSDܰݸނޯď (fcsoftrasGetSSDStatus)
#define SSD_WAR_SPR		0x01			// ߱ۯ	0: 1:ܰݸ
#define SSD_WAR_ERS		0x02			// Ϗ		0: 1:ܰݸ
#define SSD_WAR_ECC		0x04			// ECC Fail			0: 1:ܰݸ

// HDDײގw
#define HDDSTS_PRI_MAS	(0x10)			// vC}}X^w
#define HDDSTS_PRI_SRV	(0x20)			// vC}X[uw
#define HDDSTS_SEC_MAS	(0x30)			// ZJ_}X^w
#define HDDSTS_SEC_SRV	(0x40)			// ZJ_X[uw

#define HDDSTS_DRV1		(0x01)			// ~[DRIVE1w
#define HDDSTS_DRV2		(0x02)			// ~[DRIVE2w
#define HDDSTS_EXTDRV	(0x03)			// ~[ExtDRIVEw

//***********************************************************************
//	f[^\
//***********************************************************************

#pragma pack(1)

// hCoo[W (fcsoftrasGetVersion)
typedef struct _FCSOFTRAS_VAR {
	BYTE ModelNum[LEN_VAR_MODELNUM];	// fio[           (ASCII 40)
	BYTE FirmRev[LEN_VAR_FIRMREV];		// t@[EFArV (ASCII 8)
	BYTE SerialNum[LEN_VAR_SELIALNUM];	// VAio[         (ASCII 20)
} FCSOFTRAS_VAR, *PFCSOFTRAS_VAR;

// x (fcsoftrasGetTemp)
typedef struct _FCSOFTRAS_TEMP {
	BYTE TempError;						// xG[    (Bit)
	BYTE TempWarn;						// x[jO(Bit)
	signed char TempData1;				// xf[^1
	signed char TempData2;				// xf[^2
	signed char TempData3;				// xf[^3
	signed char TempData4;				// xf[^4 
} FCSOFTRAS_TEMP, *PFCSOFTRAS_TEMP;

// t@ (fcsoftrasGetFan)
typedef struct _FCSOFTRAS_FAN {
	BYTE FanError;						// t@]G[(Bit)
	BYTE FanWarn;						// t@][jO(Bit)
	WORD FanData1;						// t@]f[^1
	WORD FanData2;						// t@]f[^2
	WORD FanData3;						// t@]f[^3
	WORD FanData4;						// t@]f[^4
	WORD FanData5;						// t@]f[^5
} FCSOFTRAS_FAN, *PFCSOFTRAS_FAN;

// d (fcsoftrasGetVoltage)
typedef struct _FCSOFTRAS_VOLT {
	BYTE VoltWarn;						// d[jO(Bit)
	float VoltData1;					// df[^1
	float VoltData2;					// df[^2
	float VoltData3;					// df[^3
	float VoltData4;					// df[^4
	float VoltData5;					// df[^5
	float VoltData6;					// df[^6
	float VoltData7;					// df[^7
	float VoltData8;					// df[^8
} FCSOFTRAS_VOLT, *PFCSOFTRAS_VOLT;

// HDD (fcsoftrasGetHDDinf)
typedef struct _FCSOFTRAS_HDDINF {
	BYTE PriMasState;					// ײإϽ    (Bit)
	BYTE PriSrvState;					// ײإڰޏ  (Bit)
	BYTE SecMasState;					// إϽ    (Bit)
	BYTE SecSrvState;					// إڰޏ  (Bit)
} FCSOFTRAS_HDDINF, *PFCSOFTRAS_HDDINF;

// װޏ (fcsoftrasGetMirrorStatus)
typedef struct _FCSOFTRAS_MRRSTS {
	BYTE Status;						// װ ð
	BYTE Drv1;							// Drive1  (Bit)
	BYTE Drv2;							// Drive2  (Bit)
} FCSOFTRAS_MRRSTS, *PFCSOFTRAS_MRRSTS;

typedef struct _FCSOFTRAS_TMRRSTS {
	BYTE Status;						// װ ð
	BYTE Drv1;							// Drive1  (Bit)
	BYTE Drv2;							// Drive2  (Bit)
	BYTE Drv3;							// Drive3  (Bit)
} FCSOFTRAS_TMRRSTS, *PFCSOFTRAS_TMRRSTS;

// SMART (fcsoftrasGetSMART)
typedef struct _FCSOFTRAS_SMART {
	BYTE SmartData[LEN_SMART];			// SMARTf[^ (512byte)
} FCSOFTRAS_SMART, *PFCSOFTRAS_SMART;

typedef struct _FCSOFTRAS_SMART2 {
	BYTE SmartData[LEN_SMART2];			// SMARTf[^ ATTRIBUTE+THRESHOLD(1024byte)
} FCSOFTRAS_SMART2, *PFCSOFTRAS_SMART2;

// PCIpeBG[ (fcsoftrasGetPciError)
typedef struct _FCSOFTRAS_PCIERR {
	BYTE PciErr;						// PCIpeBG[(bit)
} FCSOFTRAS_PCIERR, *PFCSOFTRAS_PCIERR;

// oCoR (fcsoftrasGetRevRcn/fcsoftrasSetRevRcn)
typedef struct _FCSOFTRAS_REVRCN {
	BYTE Count;							// oCoR
} FCSOFTRAS_REVRCN, *PFCSOFTRAS_REVRCN;

// RTCf[^ (fcsoftrasGetRTCTime)
typedef struct _FCSOFTRAS_RTCTIME {
	BYTE Year;							// (2)
	BYTE Month;							// 
	BYTE Day;							// 
	BYTE Wday;							// j
	BYTE Hour;							// 
	BYTE Minute;						// 
	BYTE Second;						// b
} FCSOFTRAS_RTCTIME, *PFCSOFTRAS_RTCTIME;

// HDD Error Log  (fcsoftrasGetHDDErrorLog)
typedef struct _FCSOFTRAS_ERRLOG {
	BYTE ErrorLog[LEN_ERRLOG];			// ErrorLogf[^ (512x64byte)
} FCSOFTRAS_ERRLOG, *PFCSOFTRAS_ERRLOG;

// HDD Error Log 2 (fcsoftrasGetHDDErrorLog2)
typedef struct _FCSOFTRAS_ERRLOG2 {
	BYTE ErrorLog[LEN_ERRLOG2];			// ErrorLogf[^ (512x512byte)
} FCSOFTRAS_ERRLOG2, *PFCSOFTRAS_ERRLOG2;

// SSDԏ (fcsoftrasSSDStatus)
typedef struct _FCSOFTRAS_SSDINFO {
	BYTE SSDAlarm;						// SSDA[  (Bit)
	BYTE SSDWarn;						// SSD[jO(Bit)
	BYTE SsdData1;						// SSDf[^1 (XyAubNx)
	BYTE SsdData2;						// SSDf[^2 (Ϗx)
} FCSOFTRAS_SSDINFO, *PFCSOFTRAS_SSDINFO;


//***********************************************************************
//
//      ebq`r@`oh@ckk wb_`t@C
//
//      t@C  FFCRASAPI.H
//              FFCRASAPI.CPP yтckkgp`oŃCN[h
//
//***********************************************************************
                                        // `oւ̖߂l(DWORD)
#define FCRASAPI_SUCCESS    0           // 
#define FCRASAPI_FAILED     0xFFFFFFFF  // FCRAST[rXւ̗vɎs
#define FCRASAPI_DRVERR     0xFFFFFFFE  // hCoւ̗vɎsB
#define FCRASAPI_PARMERR    0xFFFFFFFD  // p[^WDTlL͈͊OłB
#define FCRASAPI_SRAMERR    0xFFFFFFFC  // ǂݏof[^t`ɂȂĂȂB

//                  // FCRAST[rXփEBhEnho^̗vR[h
//#define FCRASAPI_APWINDOWREG  1
//                  // FCRAST[rXփEBhEnho^폜̗vR[h
//#define FCRASAPI_APWINDOWDEL  2

#define FCRASAPI_NAMEDPIPE1     "\\\\.\\pipe\\fcrassv"  // pCvimoPj
#define FCRASAPI_DEVICENAME     "\\\\.\\FCRASDev"       // foCX

#define FCRASAPI_ALLSTATUSLEN   5               // SXe[^X̃TCY
#define FCRASAPI_7SEGOUTLEN     1               // 7Segment Outf[^l̃TCY

#define FCRASAPI_DIGITALINLEN   1               // Digital Inf[^l̃TCY
#define FCRASAPI_DIGITALOUTLEN  1               // Digital Outf[^l̃TCY

#define FCRASAPI_SRAMUSERLEN	(26)			// [Uf[^̏݃TCY


// ---------------------------------------------------------------------
// FCRAS T[rX̌Jwb_
// ---------------------------------------------------------------------
#if !defined( _FCRASSYS_H_ )
#define _FCRASSYS_H_

// T[rX
#define FCRAS_SERVICENAME       "FcRasService"

//
// T[rXvt (DLL -> T[rX)
//

// T[rXvtpCv
#define FCRAS_SERVICE_PIPENAME  "\\\\.\\pipe\\fcrassv"

// FCRAS T[rXւ̗vR[h
#define FCRASSV_REGIST_APWINHD  1   // EBhEnho^
#define FCRASSV_DELETE_APWINHD  2   // EBhEnho^폜

// T[rXv󂯕tpCṽf[^`
typedef struct _FCRAS_SERVICE_PIPE {
    WORD    Code;                   // vR[h
    DWORD   ApWinHd;                // [U`õEBhEnh
} FCRAS_SERVICE_PIPE, *PFCRAS_SERVICE_PIPE;

//
// A[ʒm (T[rX -> Av)
//

// A[ʒmpCv
#define FCRAS_ALARM_PIPENAME    "\\\\.\\pipe\\fcrasalm"

// A[ʒmbZ[W ID
#define WM_RASALM               (WM_USER + 0x7000)
#define WM_RASALM2              (WM_USER + 0x7001)      // *** Update 2012.11.16 ***


// ---------------------------------------------------------------------
// J[lhCǒJwb_
// ---------------------------------------------------------------------

//
// `opfoCX
//
#define FCRAS_DEVICENAME        "\\\\.\\FcRasDev"           // foCX

//
// J[lhCopfoCX
//
#define FCRAS_NT_DEVICENAME     L"\\Device\\FcRas0"         // NTfoCX
#define FCRAS_DOS_DEVICENAME    L"\\DosDevices\\FcRasDev"   // DOSfoCX

//
// Define the various device type values.  Note that values used by Microsoft
// Corporation are in the range 0-32767, and 32768-65535 are reserved for use
// by customers.
//

// Device type           -- in the "User Defined" range.
#define FILE_DEVICE_FCRAS   0x00008020

//
// Macro definition for defining IOCTL and FSCTL function control codes.  Note
// that function codes 0-0x7ff are reserved for Microsoft Corporation, and
// 0x800-0xfff are reserved for customers.
//
//
// The FCRAS device driver IOCTLs
//

#define IOCTL_FCRAS_STARTWDT \
    CTL_CODE(FILE_DEVICE_FCRAS, 0x900, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_FCRAS_STOPWDT \
    CTL_CODE(FILE_DEVICE_FCRAS, 0x910, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_FCRAS_DIN \
    CTL_CODE(FILE_DEVICE_FCRAS, 0x920, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_FCRAS_DOUT \
    CTL_CODE(FILE_DEVICE_FCRAS, 0x930, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_FCRAS_GETSTS \
    CTL_CODE(FILE_DEVICE_FCRAS, 0x940, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_FCRAS_WAITALM \
    CTL_CODE(FILE_DEVICE_FCRAS, 0x950, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_FCRAS_CANCELALM \
    CTL_CODE(FILE_DEVICE_FCRAS, 0x960, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_FCRAS_7SEGOUT \
    CTL_CODE(FILE_DEVICE_FCRAS, 0x970, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_FCRAS_ENAINT \
    CTL_CODE(FILE_DEVICE_FCRAS, 0x980, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_FCRAS_DISINT \
    CTL_CODE(FILE_DEVICE_FCRAS, 0x990, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_FCRAS_START1MT \
    CTL_CODE(FILE_DEVICE_FCRAS, 0x9a0, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_FCRAS_STOP1MT \
    CTL_CODE(FILE_DEVICE_FCRAS, 0x9b0, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_FCRAS_DIP \
	CTL_CODE(FILE_DEVICE_FCRAS, 0x9c0, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_FCRAS_VER \
	CTL_CODE(FILE_DEVICE_FCRAS, 0x9d0, METHOD_BUFFERED, FILE_ANY_ACCESS)

#define IOCTL_FCRASIO_EXTLIMITSET \
	CTL_CODE(FILE_DEVICE_FCRAS, 0x9e0, METHOD_BUFFERED, FILE_ANY_ACCESS)
#define IOCTL_FCRASIO_INTLIMITSET \
	CTL_CODE(FILE_DEVICE_FCRAS, 0x9f0, METHOD_BUFFERED, FILE_ANY_ACCESS)

#define IOCTL_FCRASIO_TEST \
	CTL_CODE(FILE_DEVICE_FCRAS, 0xb00, METHOD_BUFFERED, FILE_ANY_ACCESS)

// Nݒ
#define IOCTL_FCRASIO_SRAM_INIT_TIME \
	CTL_CODE(FILE_DEVICE_FCRAS, 0xb10, METHOD_BUFFERED, FILE_ANY_ACCESS)

// SRAM[h
#define IOCTL_FCRASIO_SRAMREAD1 \
	CTL_CODE(FILE_DEVICE_FCRAS, 0xb11, METHOD_BUFFERED, FILE_ANY_ACCESS)
// SRAMCg
#define IOCTL_FCRASIO_SRAMWRITE1 \
	CTL_CODE(FILE_DEVICE_FCRAS, 0xb12, METHOD_BUFFERED, FILE_ANY_ACCESS)

// SRAM  [h
#define IOCTL_FCRASIO_SRAM_SEQREAD \
	CTL_CODE(FILE_DEVICE_FCRAS, 0xb13, METHOD_BUFFERED, FILE_ANY_ACCESS)
// SRAM  Cg
#define IOCTL_FCRASIO_SRAM_SEQWRITE \
	CTL_CODE(FILE_DEVICE_FCRAS, 0xb14, METHOD_BUFFERED, FILE_ANY_ACCESS)

// SRAMGȀ
#define IOCTL_FCRASIO_SRAM_INIT_RAM \
	CTL_CODE(FILE_DEVICE_FCRAS, 0xb15, METHOD_BUFFERED, FILE_ANY_ACCESS)

// LCD\f[^Cg
#define IOCTL_FCRASIO_LCDWRITE \
	CTL_CODE(FILE_DEVICE_FCRAS, 0xb16, METHOD_BUFFERED, FILE_ANY_ACCESS)



// ---------------------------------------------------------------------
// IO CTLp\̒`
// ---------------------------------------------------------------------

#define RAS_IFI_LNG         8   // ͗p FCRAS_IF (Byte)
#define RAS_IF_LNG          (sizeof(FCRAS_IF))  // FCRAS_IF (Byte)
#define RAS_SRAM_IF_LNG		(sizeof(DWORD)*2)	//  FCRAS_SRAM_IF f[^TCY
#define RAS_SRAMSEQ_IF_LNG  (sizeof(FCRAS_SRAMSEQ_IF))

#pragma pack(1)
typedef struct _FCRAS_IF {
    BYTE LED7Segment;           // [ RESERVE ]
    WORD WDT;                   // WDTZbgl
    BYTE DigitalOut;            // fW^o̓f[^
    BYTE Reserve1[4];           // [ RESERVE ]
    BYTE Status1;               // A[
    BYTE Status2;               // WDT, 荞݃Cl[u, P^C}
    BYTE Status3;               // OfW^o̓f[^
    BYTE Status4;               // WDTZbgl (High)
    BYTE Status5;               // WDTZbgl (Low)
    BYTE Status6;               // fW^o̓f[^
    BYTE Status7;               // AiO̓[h(H/WeXgp)
    BYTE Status8;               // xl
    BYTE Status9;               // P^C}JE^l
    BYTE DigitalIn;             // fW^̓f[^
    BYTE Reserve2[6];           // [ RESERVE ]
	BYTE ExtLimit;				// Oxl
	BYTE IntLimit;				// xl
    BYTE Status10;				// A[̓j^Q
    BYTE Status11;				// xl
    BYTE Status12;				// Ox㏸ol
    BYTE Status13;				// x㏸ol
    BYTE Status14;				// fBbvXCb`P
    BYTE Status15;				// fBbvXCb`Q
    BYTE Status16;				// A[̓j^
    BYTE Status17;				// [eXgA[
} FCRAS_IF, *PFCRAS_IF;

//SRAMpANZXpf[^(ėp)
typedef struct _FCRAS_SRAM_IF {
	DWORD	dwOffset;
	DWORD	dwSize;
	BYTE	data[1];
} FCRAS_SRAM_IF, *PFCRAS_SRAM_IF;

//SRAMpANZXpf[^(p)
typedef struct _FCRAS_SRAMSEQ_IF {
	DWORD	dwOffset;			// [h̃ItZbgw
	BYTE	bMode;				// 1:[Ü@2:VXë
	BYTE	data[64];			// /ǂݍ݃f[^
} FCRAS_SRAMSEQ_IF, *PFCRAS_SRAMSEQ_IF;

typedef struct _FCRAS_DATE_IF {
	BYTE bYear;
	BYTE bMonth;
	BYTE bDay;
	BYTE bHour;
	BYTE bMinute;
	BYTE bSecond;
} FCRAS_DATE_IF, *PFCRAS_DATE_IF;

typedef struct _FCRAS_STATUS_1TO6 {
    BYTE Status1;               // A[
    BYTE Status2;               // WDT, 荞݃Cl[u, P^C}
    BYTE Status3;               // OfW^o̓f[^
    BYTE Status6;               // fW^o̓f[^
    BYTE Status7;               // xZT~[O{[hA[̓j^
    BYTE Status16;              // A[̓j^2
} FCRAS_STATUS_1TO6;

//LCD\pf[^
typedef struct _LCDDATA {
	BYTE	udata[16];			// 㑤݃f[^
	BYTE	ddata[10];			// ݃f[^
} LCDDATA, *PLCDDATA;
typedef struct _FCRAS_LCDDISP_IF {
	BYTE	bDspNum;			// LCDޯ̧ԍ
	BYTE	bMode;				// 1:\@0:
	LCDDATA data;				// ݃f[^\
} FCRAS_LCDDISP_IF, *PFCRAS_LCDDISP_IF;

#pragma pack( )


// ---------------------------------------------------------------------
// SRAM@}bv
// ---------------------------------------------------------------------


#define FCSRAM_USER_START			(0x00000000)		// [Ü̊JnAhX(݃GA)
#define FCSRAM_USER_END				(0x0001ffff)		// [Ü̏IAhX
#define FCSRAM_SYSTEM_START			(0x00020000)		// VXëJnAhX(݃GA)
#define FCSRAM_SYSTEM_END			(0x0003ffff)		// VXëIAhX
#define	FCSRAM_FREE_START			(0x00040000)		// 󂫗̈JnAhX
#define	FCSRAM_FREE_END				(0x0007FDFF)		// 󂫗̈IAhX
#define FCSRAM_ADMIN_START			(0x0007FE00)		// Ǘ̈JnAhX
#define FCSRAM_ADMIN_END			(0x0007FFFF)		// Ǘ̈IAhX

// ݗp`
#define FCSRAM_RECORD_SIZE			(0x20)				// 1R[h̃f[^TCY
#define FCSRAM_RECORD_SIZE_SYS		(0x40)				// VXep1R[h̃f[^TCY
#define	FCSRAM_SEQMODE_USER			(0)					// [Ȕ݃[h
#define	FCSRAM_SEQMODE_SYSTEM		(1)					// VXȅ݃[h
#define	FCSRAM_DATA_SIZE			(6)					// tf[^̃TCY(6oCg)

// VXë
#define FCSRAM_ADMIN_RUN			(0x0000)			// VXeJniT[rXJn)
#define	FCSRAM_ADMIN_COUNT			(0x0008)			// VXeJn̗ݐώ
#define	FCSRAM_ADMIN_USER_CUR		(0x0020)			// [Ü̃Jg|C^
#define	FCSRAM_ADMIN_USER_NEXT		(0x0024)			// [Ü̃lNXg|C^
#define FCSRAM_ADMIN_USER_INIT		(0x0028)			// [Ü揉JE^
#define FCSRAM_ADMIN_USER_ERR		(0x002c)			// [Ü|C^G[JE^
#define	FCSRAM_ADMIN_SYSTEM_CUR		(0x0030)			// VXë̃Jg|C^
#define	FCSRAM_ADMIN_SYSTEM_NEXT	(0x0034)			// VXë̃lNXg|C^
#define FCSRAM_ADMIN_SYSTEM_INIT	(0x0038)			// VXë揉JE^
#define FCSRAM_ADMIN_SYSTEM_ERR		(0x003c)			// VXë|C^G[JE^

#endif
// ***

#pragma pack( )
